This invention generally relates to metallic electrodeposition on semiconductor surfaces and associated processes and more particularly to a method for reducing wafer edge defects during and following an electrodeposition process.
Sub-micron multi-level metallization is one of the key technologies for the next generation of ultra large scale integration (ULSI). The multilevel interconnects that lie at the heart of this technology require planarization of interconnect features formed in high aspect ratio apertures, including contacts, vias, metal interconnect lines and other features. Reliable formation of these interconnect features is very important to the success of ULSI and to the continued effort to increase circuit density and quality on individual substrates and die.
Copper and copper alloys have become the metal of choice for filling sub-micron, high aspect ratio interconnect features on semiconductor substrates. Copper and its alloys have lower resistivity and higher electromigration resistance compared to other metals such as, for example, aluminum. These characteristics are critical for achieving higher current densities increased device speed.
As circuit densities increase, the widths of vias, contacts, metal interconnect lines, and other features, decrease to sub-micron dimensions, whereas the thickness of the dielectric layers, through the use low-k (low dielectric constant) materials, has remained substantially constant. Consequently, the aspect ratios for the features, i.e., their height divided by width, has increased thereby creating additional challenges in adequately filling the sub-micron features with, for example, copper metal. Many traditional deposition processes such as chemical vapor deposition (CVD) have difficulty filling increasingly high aspect ratio features, for example, where the aspect ratio exceeds 2:1, and particularly where it exceeds 4:1.
As a result of these process limitations, electroplating or electrodeposition, which has previously been limited to the fabrication of patterns on circuit boards, is now emerging as a preferable method for filling metal interconnects structures such as via openings (holes) and trench line openings on semiconductor devices. Typically, electroplating uses an electrolyte including positively charged ions of deposition material, for example metal ions, in contact with a negatively charged substrate (cathode) having a source of electrons to deposit (plate out) the metal ions onto the charged substrate, for example, a semiconductor wafer. A thin metal layer (seed layer) is first deposited on the semiconductor wafer to form a liner in high aspect ratio anisotropically etched features to provide a continuous electrical path across the surfaces. An electrical current is supplied to the seed layer whereby the semiconductor wafer surface including etched features are electroplated with an appropriate metal, for example, aluminum or copper, to fill the features.
One exemplary process for forming a series of interconnected multiple layers, for example, is a damascene or dual damascene process. Although there are several different manufacturing methods for manufacturing damascene structures, all such methods employ a series of photolithographic masking and anisotropic etching steps, typically by a reactive ion etch (RIE). In the typical multilayer semiconductor manufacturing process, for example, a series insulating layers are deposited to include a series of interconnecting metallization structures such as vias and metal line interconnects to electrically interconnect areas within the multilayer device and contact layers to interconnect the various devices on the chip surface. In most devices, pluralities of vias are separated from one another along the semiconductor wafer and selectively interconnect conductive regions between layers of a multilayer device. Metal interconnect lines typically serve to selectively interconnect conductive regions within a layer of a multilayer device. Vias and metal interconnect lines are selectively interconnected in order to form the necessary electrical connections.
In filling the via openings and trench line openings with metal, for example, copper, electroplating is a preferable method to achieve superior step coverage of sub-micron etched features. The method generally includes first depositing a barrier layer over the etched opening surfaces, such as via openings and trench line openings, depositing a metal seed layer, for example copper, over the barrier layer, and then electroplating a metal, for example copper, over the seed layer to fill the etched features to form conductive vias and trench lines. Finally, the electro deposited layer and the dielectric layers are planarized, for example, by chemical mechanical polishing (CMP), to define a conductive interconnect feature.
Metal electroplating (electrodeposition) in general is a well-known art and can be achieved by a variety of techniques. Common designs of cells for electroplating a metal on semiconductor wafers involve positioning the plating surface of the semiconductor wafer within an electrolyte solution including an anode with the electrolyte impinging perpendicularly on the plating surface. The plating surface is contacted with an electrical power source forming the cathode of the plating system such that ions in the plating solution deposit on the conductive portion of the plating surface, for example a semiconductor wafer surface.
For example, referring to FIG. 1 is shown a portion of a semiconductor process surface showing a cross sectional side view of a dual damascene structure 10 made up of a via portion 10A and an overlying trench line portion 10B. The dual damascene structure 10 is formed in an insulating layer 12 having, for example, a barrier layer 14A of TaN nitride conformally deposited to over the via and trench sidewalls and via bottom portion and an overlying conformally deposited seed layer 14B, for example, copper typically deposited by physical vapor deposition (PVD) or chemical vapor deposition (CVD). During a typical electroplating process a major portion of the damascene structure 10 is filled with, for example, copper to form copper layer 18 by a high current electrodeposition process. Following the electro-deposition process, a chemical mechanical polishing (CMP) process is carried out to polish back the excess copper layer 18 to achieve a planarized surface.
More recent electroplating processes use self contained assemblies where the anode and semiconductor wafer are in close proximity to carry out both electroplating and electropolishing. Typically the semiconductor wafer surface is spaced apart from the anode in the electroplating solution during electrodeposition and contacts the anode during the electropolishing process where the semiconductor wafer becomes the anode and the anode assembly acts as a cathode. Following the electrodeposition process and electropolishing process, the semiconductor wafer surface is rinsed and dried. During the various processes the semiconductor wafer is attached to a wafer chuck for holding the wafer during the various processes. According to the prior art, a sealing means, typically sealing ring applied around the periphery of the wafer electrodeposition surface has been used to prevent process solutions, including the electrolyte to migrate around the wafer edge and contaminate the backside of the process wafer.
One problem with the prior art electrodeposition (electroplating) methods, is that the sealing means sealing the process side of the wafer is not fully effective in sealing against process solution leakage. For example, the sealing means typically forms leaks between a sealing ring and the wafer process surface which allow the process solutions, for example, the electrolyte or polishing solutions to migrate through to contaminate the backside of the wafer. Such contamination adversely affects downstream processes and reduces throughput and yield.
These and other shortcomings demonstrate a need in the semiconductor processing art to develop a method for electrodeposition whereby contamination of the process wafer backside is reduced or avoided.
It is therefore an object of the invention to provide a method for electrodeposition whereby for electrodeposition whereby contamination of the process wafer backside is reduced or avoided while overcoming other shortcomings and deficiencies in the prior art.
To achieve the foregoing and other objects, and in accordance with the purposes of the present invention, as embodied and broadly described herein, the present invention provides a method for reducing or avoiding semiconductor wafer peripheral defects and contamination during and following electrode position.
In a first embodiment, the method includes providing a wafer chuck assembly sealably attached to a back side of a semiconductor wafer leaving an exposed peripheral portion of adjacent the back side of the semiconductor wafer edge the backside parallel to a front side of the semiconductor wafer comprising a process surface; contacting at least the semiconductor wafer process surface with the process solution for processing while simultaneously spinning the semiconductor wafer; and, simultaneously directing a pressurized flow of gas onto the exposed peripheral portion such that the pressurized flow of gas covers the exposed peripheral portion including being radially directed outward toward the periphery of over the semiconductor wafer edge.
These and other embodiments, aspects and features of the invention will be better understood from a detailed description of the preferred embodiments of the invention which are further described below in conjunction with the accompanying Figures.